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Freescale Semiconductor /MK26F18 /USBPHY /CTRL_TOG

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Interpret as CTRL_TOG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENHOSTDISCONDETECT)ENHOSTDISCONDETECT 0 (HOSTDISCONDETECT_IRQ)HOSTDISCONDETECT_IRQ 0 (0)ENDEVPLUGINDET 0 (DEVPLUGIN_IRQ)DEVPLUGIN_IRQ 0 (ENUTMILEVEL2)ENUTMILEVEL2 0 (ENUTMILEVEL3)ENUTMILEVEL3 0 (AUTORESUME_EN)AUTORESUME_EN 0 (ENAUTOCLR_CLKGATE)ENAUTOCLR_CLKGATE 0 (ENAUTOCLR_PHY_PWD)ENAUTOCLR_PHY_PWD 0 (FSDLL_RST_EN)FSDLL_RST_EN 0 (OTG_ID_VALUE)OTG_ID_VALUE 0 (HOST_FORCE_LS_SE0)HOST_FORCE_LS_SE0 0 (UTMI_SUSPENDM)UTMI_SUSPENDM 0 (CLKGATE)CLKGATE 0 (SFTRST)SFTRST

ENDEVPLUGINDET=0

Description

USB PHY General Control Register

Fields

ENHOSTDISCONDETECT

For host mode, enables high-speed disconnect detector
HOSTDISCONDETECT_IRQ

Indicates that the device has disconnected in High-Speed mode
ENDEVPLUGINDET

Enables non-standard resistive plugged-in detection

0 (0): Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)

1 (1): Enables 200kohm pullup resistors on USB_DP and USB_DM pins
DEVPLUGIN_IRQ

Indicates that the device is connected
ENUTMILEVEL2

Enables UTMI+ Level 2 operation for the USB HS PHY
ENUTMILEVEL3

Enables UTMI+ Level 3 operation for the USB HS PHY
AUTORESUME_EN

Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
ENAUTOCLR_CLKGATE

Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
ENAUTOCLR_PHY_PWD

Enables the feature to auto-clear the PWD register bits in USBPHY_PWD if there is wakeup event while USB is suspended
FSDLL_RST_EN

Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
OTG_ID_VALUE

Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle
HOST_FORCE_LS_SE0

Forces the next FS packet that is transmitted to have a EOP with low-speed timing
UTMI_SUSPENDM

Used by the PHY to indicate a powered-down state
CLKGATE

Gate UTMI Clocks
SFTRST

Writing a 1 to this bit will soft-reset the USBPHY_PWD, USBPHY_TX, USBPHY_RX, and USBPHY_CTRL registers

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data